1. Field of the Invention
The present invention relates to a microprocessor and, more particularly, to a microprocessor for structuring a high reliability data processing system.
2. Description of Related Art
As one technique for structuring a high reliability data processing system, it is known in the art to add redundant information to data. In a system employing a parity bit as redundant information, data read out of a memory is checked for validity by checking the parity bit information added thereto. This data processed by the microprocessor is written into the memory together with the parity bit information.
Referring to FIG. 1, there is shown such a prior art data processing system. A microprocessor 701 is interconnected through a system control bus 704, a system address bus 705 and a system data bus 706 to a program/data memory 702 storing a program and operand data to be executed and processed. The program and data stored in the memory 702 are called hereinafter "data". There are further provided a parity bit memory 703 and a parity control circuit 708. The memory 703 is connected to the system control and address buses 704 and 705, and the control circuit 708 is connected to the system control and data buses 704 and 706. The memory 703 and the control circuit 708 are interconnected through a parity bit line 707. The control circuit 708 supplied a data valid/invalid indication signal 709 and a ready signal 710.
In a data read operation, the microprocessor 701 accesses to desired addresses of the memories 702 and 703 by means of the control and address buses 704 and 705. The data read out of the accessed address is transferred via the data bus 706 to the microprocessor 701 and further to the parity control circuit 708. Moreover, parity bit information added to the data read out of the memory 702 is read out from the parity bit memory 703 and transferred to the control circuit 708 via the line 707. The parity control circuit 708 calculates a syndrome of the data supplied thereto and compares the calculation resultant with the parity bit information. During the calculation, the control circuit 708 changes the ready signal 710 to an inactive level to inform the microprocessor 701 of the circuit 708 state of calculating. When the calculation is completed, the control circuit 708 changes the ready signal 710 to an active level and informs, by the signal 709, the microprocessor 701 whether or not the data read out of the memory 702 is valid.
In a data write operation, the microprocessor 701 accesses desired addresses of the memories 702 and 703 by means of the control and address buses 704 and 705 and transfers data to be written onto the data bus 706. This data is written into the accessed address of the memory 702 and further supplied to the parity control circuit 708. The circuit 708 calculates a syndrome of the data and produces parity bit information which is in turn written into the accessed address of the memory 703 through the line 707. During the syndrome calculation, the circuit 708 supplied the inactive level ready signal 710 to the microprocessor 701.
Thus, a high reliability system can be structured. As apparent from the above description, however, an effective memory access time is determined by the summation of an access time required by the memory 702 and a syndrome calculation time required by the parity control circuit 708. For this reason, the microprocessor cannot perform a data processing operation at a high speed to reduce the performance of the system.